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general description the max6960?ax6963 are compact cathode-row dis- play drivers that interface microprocessors to 8 x 8 dot- matrix red, green, and yellow (r,g,y) led displays through a high-speed 4-wire serial interface. the max6960?ax6963 drive two monocolor 8 x 8 matrix displays, or a single rgy 8 x 8 matrix display with no external components. the driver can also be used with external pass transistors to control red, green, blue (rgb) and other displays at higher currents and voltages. the max6960?ax6963 feature open- and short-circuit led detection, and provide both analog and digital tile segment current calibration to allow 8 x 8 displays from different batches to be compensated or color matched. a local 3-wire bus synchronizes multiple interconnected max6960?ax6963s and automatically allocates memory map addresses to suit the user? display-panel architecture. the max6960?ax6963s?4-wire interface connects mul- tiple drivers, with display memory mapping shared and allocated among the drivers. a single global write opera- tion can send a command to all max6960s in a panel. the max6963 drives monocolor displays with two-step intensity control. the max6962 drives monocolor displays with two-step or four-step intensity control. the max6961 drives monocolor or rgy displays with two-step intensity control. the max6960 drives monocolor or rgy displays with two-step or four-step intensity control. features ? 2.7v to 3.6v operation ? high-speed 20mhz serial interface ? trimmed 40ma or 20ma peak segment current ? directly drives either two monocolor or one rgy cathode-row 8 x 8 matrix displays ? analog digit-by-digit segment current calibration ? digital digit-by-digit segment current calibration ? 256-step panel intensity control (all drivers) ? four steps per color pixel-level intensity control ? open/short led detection ? burst white to display memory planes ? global command access all devices ? can control rgb panels or higher current/voltage panels with external pass transistors ? multiple display data planes ease animation ? automatic plane switching from 63 planes per second to one plane every 63s, with interrupt ? slew-rate-limited segment drivers for lower emi ? driver switching timing can be spread between multiple drivers to flatten power-supply peak demand ? low-power shutdown with full data retention ? -40? to +125? temperature range max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ________________________________________________________________ maxim integrated products 1 ordering information 19-3696; rev 3; 6/07 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. pin configurations continued at end of data sheet. evaluation kit available part temp range pin-package pkg code m a x6 9 6 0 am h -40 c to +125 c 44 mqfp m ax6960ath -40 c to +125 c 44 tqfn - e p * t4477- 3 m a x6 9 6 1 am h -40 c to +125 c 44 mqfp m ax6961ath -40 c to +125 c 44 tqfn - e p * t4477-3 m a x6 9 6 2 am h -40 c to +125 c 44 mqfp m ax6962ath -40 c to +125 c 44 tqfn - e p * t4477-3 m a x6 9 6 3 am h -40 c to +125 c 44 mqfp m ax6963ath -40 c to +125 c 44 tqfn - e p * t4477-3 col13 col12 col11 col10 col9 v+ col8 col7 col6 col5 col4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 gnd osc cs din dout clk rst col1 col2 col3 v+ gnd riset1 riset0 addclk addin addout v+ col16 col15 col14 v+ mqfp max6960-max6963 top view pin configurations applications message boards industrial controls gaming machines audio/video equipment * ep = exposed paddle.
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = 2.7v to 3.6v, t a = t min to t max , typical values at v+ = 3.3v, t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. (voltage with respect to gnd.) v+ .............................................................................-0.3v to +4v all other pins................................................-0.3v to (v+ + 0.3v) row1?ow8 sink current ..............................................750ma col1?ol16 source current ...........................................48ma continuous power dissipation (t a = +70?) 44-pin mqfp (derate 12.7 mw/? over +70?) ...............................1012mw 44-pin tqfn (derate 27mw/? over +70?) ...................................2162mw operating temperature range (t min to t max ) ..............................................-40? to +125? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units operating supply voltage v+ 2.7 3.6 v t a = +25? 250 375 t a = t min to +85? 500 shutdown supply current i shdn shutdown mode, all digital inputs at v+ or gnd t a = t min to t max 600 ? t a = +25? 7.5 9 t a = t min to +85? 10 operating supply current i+ intensity set to full, no display load connected t a = t min to t max 11 ma master clock frequency f osc 1.0 8.5 mhz dead-clock protection frequency f osc 50 90.5 200 khz osc high time t ch 40 ns osc low time t cl 40 ns t a = +25? 38 40 42 t a = t min to +85? 37 43 v led = 2.3v, v+ = 3.15v to 3.6v, current = high t a = t min to t max 37 44 t a = +25? 19 20 21 t a = t min to +85? 18.5 21.5 anode column source current col1?ol16 i seg v led = 2.3v, v+ = 2.7v to 3.6v, current = low t a = t min to t max 18.5 22.0 ma v led = 2.3v, v+ = 3.15v to 3.6v, current = high 200 anode column source-current temperature variation col1?ol16 i tc v led = 2.2v, v+ = 2.7v to 3.3v, current = low 200 ppm/? segment current slew rate i seg / tt a = +25? 30 ma/?
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 2.7v to 3.6v, t a = t min to t max , typical values at v+ = 3.3v, t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units logic inputs and outputs input leakage current din, clk, cs , osc, addin, addclk, rst i ih , i il -100 5 +100 na logic-high input voltage din, clk, cs , osc, addin, addclk, rst v ihi 0.7 x v+ v logic-low input voltage din, clk, cs , osc, addin, addclk, rst v ilo 0.3 x v+ v dout output rise and fall times t ftdo c load = 100pf 10 ns dout output high voltage v ohdo i source = 20ma v+ - 0.3 v dout output low voltage v oldo i sink = 20ma 0.3 v addout output high voltage v ohado i source = 500? v+ - 0.3 v addout output low voltage v olado i sink = 500? 0.3 v addclk output high voltage v ohack i source = 2.5ma v+ - 0.3 v addclk output low voltage v olack i sink = 2.5ma 0.3 v timing characteristics clk clock period t cp 50 ns clk pulse-width high t ch 22 ns clk pulse-width low t cl 22 ns cs fall to clk rise setup time t css 12.5 ns clk rise to cs rise hold time t csh 0ns din setup time t ds 12.5 ns din hold time t dh 10 ns output data propagation delay t do 22 ns minimum cs pulse high t csw 25 ns note 1: all parameters are tested at t a = +25?. specifications over temperature are guaranteed by design.
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 4 _______________________________________________________________________________________ typical operating characteristics (t a = +25?, unless otherwise noted.) operating supply current vs. temperature max6960 toc01 temperature ( c) supply current (ma) 92 59 26 -7 7.2 7.4 7.6 7.8 8.0 7.0 -40 125 3.6v 3.3v 2.7v shutdown supply current vs. temperature max6960 toc02 temperature ( c) supply current (ma) 92 59 26 -7 0.1 0.2 0.3 0.4 0 -40 125 3.6v 3.3v 2.7v dead-clock oscillator vs. supply voltage max6960 toc03 supply voltage (v) dead-clock oscillator 3.38 3.16 2.94 2.72 85 90 95 100 80 2.50 3.60 +25 c -40 c +125 c peak-output source current vs. supply voltage (high-current mode) max6960 toc04 supply voltage (v) peak-output current (ma) 3.4 3.1 2.8 37 39 41 43 45 35 2.5 3.7 2.3v led peak-output source current vs.supply voltage (low-current mode) max6960 toc05 supply voltage (v) peak-output current (ma) 3.5 3.3 3.1 2.9 2.7 18 19 20 21 22 17 2.5 3.7 2.2v led peak-output source current vs. temperature (high-current mode) max6960 toc06 temperature ( c) peak-output current (ma) 92 59 26 -7 39.6 40.0 40.4 40.8 39.2 -40 125 2.3v led 3.6v 3.3v 3.15v typical operating characteristics
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers _______________________________________________________________________________________ 5 pin description pin mqfp tqfn name function 1, 6, 11, 12, 44 1, 6, 11, 12, 44 gnd ground 2?, 7?0 2?, 7?0 row1?ow8 le d c athod e d r i ver s. row 1 to ro w 8 outp uts si nk cur r ent fr om the d i sp l ay' s cathod e r ow s. 13 13 osc multiplex clock input. drive osc with a 1mhz to 8.5mhz cmos clock. 14 14 cs chip-select input. serial data is loaded into the shift register when cs is low. data is loaded into the data latch on cs 's rising edge. 15 15 din serial-data input. data from din loads into the internal shift register on clk's rising edge. 16 16 dout serial-data output. the output is tri-state. 17 17 clk serial-clock input. on clk's rising edge data shifts into the internal shift register. 18 18 rst reset input. hold rst low until at least 50ms after all interconnected max6960s are powered up. 19, 20, 21, 23?7, 29?3, 35, 36, 37 19, 20, 21, 23?7, 29?3, 35, 36, 37 col1?ol16 led anode drivers. col1 to col16 outputs source current into the display's anode columns. 22, 28, 34, 38 22, 28, 34, 38 v+ positive supply voltage. bypass v+ to gnd with a single 47? bulk capacitor per chip plus a 0.1? ceramic capacitor per v+. 39 39 addout address-data output. connect addout to addin of the next max6960. use addout of the last max6960 as a plane change interrupt output. 40 40 addin address-data input. for first max6960, connect addin to v+. for other max6960s, connect addin to addout of the preceding max6960. 41 41 addclk address-clock input/output. connect addclk of all max6960 drivers together, ensuring that only one max6960's addin input is connected to v+. 42 42 riset0 digit 0 current setting. connect riset0 to gnd to program all of digit 0's segment currents to 40ma. leave riset0 open circuit to program all of digit 0's segment currents to 20ma. connect riset0 to gnd through a fixed or variable resistor to adjust all of digit 0's segment currents between 20ma and 40ma. 43 43 riset1 digit 1 current setting. connect riset1 to gnd to program all of digit 1's segment currents to 40ma. leave riset1 open circuit to program all of digit 1's segment currents to 20ma. connect riset1 to gnd through a fixed or variable resistor to adjust all of digit 1's segment currents between 20ma and 40ma. ep ep exposed pad on package underside. connect to gnd.
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 6 _______________________________________________________________________________________ quick-start guide selecting the appropriate driver the max6960?ax6963 matrix led drivers are avail- able in four versions, with different levels of functionality (table 1). the two-part id bits in the fault and device id register (table 32) identify the driver type to the inter- face software. the id bits may be of use if the same panel software is used to drive more than one type of display panel, because the software can automatically detect the panel type. this data sheet uses the generic name max6960 to refer to the family of four parts max6960 through max6963, unless there is a specific difference to discuss. the purpose of this quick-start guide is to provide an overview of the capabilities of the max6960 so that the driver can be easily evaluated for a particular applica- tion, without fighting through a complex data sheet. terminology pixel: one ?oint?on a display. comprises one led for a monocolor display, two leds for an rgy dis- play, and three leds for an rgb display. monocolor: display has only one color, typically red for low-cost signs or orange for traffic signs. varying the current through the led changes the intensity of the red. available functions part rgb 2 bits per pixel * rgb 1 bit per pixel * rgy 2 bits per pixel rgy 1 bit per pixel monocolor 2 bits per pixel monocolor 1 bit per pixel register limitations max6960 ? none. max6961 pi bit (bit d7) in global panel configuration register is fixed at 0 (table 22). max6962 ? ? c bit (bit d6) in global panel configuration register is fixed at 0 (table 21). max6963 c bit (bit d6) in global panel configuration register is fixed at 0 (table 21). pi bit (bit d7) in global panel configuration register is fixed at 0 (table 22). table 1. levels of functionality display configuration maximum pixel count example maximum panel (pixels) monocolor 32,768 256 x 128 rgy 16,384 256 x 64 rgb 32,768 (3 buses required; see figure 17) 128 x 85 table 2. maximum display matrix on a single 4-wire interface 256 drivers on 4-wire interface, 50 frames per second update rate display-memory-access method 1-bit-per-pixel intensity control (mbps) 2-bits-per-pixel intensity control (mbps) 8-bit indirect display memory addressing 1.64 3.28 24-bit direct display memory addressing 4.92 9.83 table 3. 4-wire interface speed requirements for animation * when operated per figure 17.
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers _______________________________________________________________________________________ 7 bicolor: literally means two color, and usually refers to leds built with two led dice of different colors, typically red and green or red and orange/yellow. tricolor: literally means three color, and can refer to leds built with three led dice of different colors, typi- cally red, green, and blue. the term is also used to refer to a display built with bicolor leds, because there are three main colors available (red, green, yellow). rgy: display uses one red led (r) and one green led (g) per pixel. when both red and green leds are lit, the resulting color is yellow (y). varying the current through the leds changes the intensity of the pixel and changes the color from red through shades of orange and yellow to green. rgb: display uses one red led (r), one green led (g), and one blue led (b) per pixel. varying the cur- rent through the leds changes the intensity of the pixel and changes the color through many shades limited by the current control resolution. max6960 applications the max6960 is a multiplexed, constant-current led driver intended for high-efficiency indoor signage and message boards. the high efficiency arises because the driver operates from a 3.3v nominal supply with minimal voltage head- room required across the driver output stages. the problem of removing heat from even a small display is therefore minimized. the maximum peak led drive current is 40ma, which when multiplexed eight ways, provides an average cur- rent of 5ma per led. this current drive is expected to be adequate for indoor applications, but inadequate for outdoor signs operating in direct sun. the max6960 directly drives monocolor (typically red or orange/yellow) or rgy (typically red/green or red/yellow) graphic displays using leds with a forward voltage drop up to 2.5v. blue leds and some green leds cannot be driven directly because of their high forward voltage drop (around 3.5v to 4.5v). for these displays, the max6960 can be used as a graphic con- troller, just as it can be used for applications requiring higher peak segment currents, and in rgb panels needing a higher driver voltage for the blue leds. in these cases, the max6960 can be used with external drive transistors to control anode-row displays, with all driver features including pixel-level intensity control still available (see the applications information section and figure 17). display intensity control five levels of intensity control are provided: a 256-step pwm panel intensity adjustment sets all max6960s simultaneously as a global panel bright- ness control (table 27). the 256-step resolution is fine enough to allow fade-in/fade-out graphic effects, as well as provide a means for compensating a panel for background lighting. a 2-bits-per-pixel intensity control allows four bright- ness levels to be set independently per pixel. the pixel-level intensity control can be set to be either arithmetic (off, 1/3, 2/3, full) or geometric (off, 1/4, 1/2, full) for full flexibility (table 24), and allows four colors to be displayed on monocolor panels, or 16 colors to be displayed on rgy panels, or 64 colors to be displayed on rgb panels. the led drive current can be selected between either a 40ma peak per segment and a lower 20ma peak current on a digit-by-digit basis using the r iset0 and r iset1 pins. the lower (20ma) current may be the better choice to drive high-efficiency dis- plays, and this setting allows the max6960 to oper- ate from a supply voltage as low as 2.7v. the led drive current can be adjusted between 40ma and 20ma peak current on a digit-by-digit basis using fixed or adjustable resistors connected from the r iset0 and r iset1 pins to gnd. these con- trols enable analog relative adjustments in digit intensity, typically to calibrate digits from different batches, or to color balance rgy displays. the digit intensity controls allow each digit? operat- ing current to be scaled down in 256 steps from the global panel intensity adjustment. the effective oper- ating current for each digit becomes n/256th of the panel intensity value. these controls enable digital relative adjustments in digit intensity in addition to the analog approach outlined above. display size limitations the maximum display size that can be handled by a single 4-wire serial interface is given in table 2, which is for the maximum 256 interconnected max6960s. larger display panels can be designed using a sepa- rate cs line for each group of (up to) 256 max6960s. each group would also have its own local 3-wire bus to allocate the driver addresses. the 4-wire interface speeds requirement when continuously updating dis- play memory for high-speed animations is given in table 3.
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 8 _______________________________________________________________________________________ software control the hardware features are designed to simplify the software interface and eliminate software timing depen- dencies: two or four planes of display memory are stored, allowing images to be preloaded into the max6960 max6963 frame memory. animation timing is built in, sequencing through the two or four planes automatically. system software has to update the upcoming plane(s) with new data ahead of time, but do not be concerned about exact timing. the frame rate is adjustable to as fast as 63 frames a second for animations, or to as slow as one frame change every 63s for advertising sequencing. multiple max6960s interconnect and share display memory so that the software ?ees?the display as memory-mapped planes of contiguous ram. global commands that need to be received and acted on by every max6960 in a panel do just that, with one write. hardware design a max6960 normally drives an 8 x 16 led matrix, com- prising 8 cathode rows and 16 anode columns, or 8 anode rows and 16 cathode columns with external drivers. the max6960 standard wiring connection to either two monocolor 8 x 8 digits, or to a single rgy 8 x 8 digit is shown in table 4. figure 3 shows the display pin naming. figures 1 and 2 show example displays with the max6960 drivers connecting to monocolor and rgy pan- els. figure 4 shows how the display memory maps to the physical pixels on the display panel, provided that the max6960 drivers are interconnected correctly in a raster- like manner from top left of the panel to bottom right. detailed description overview the max6960 is an led display driver capable of driving either two monocolor 8 x 8 cathode-row matrix digits, or a single rgy 8 x 8 cathode-row matrix digit. the architec- ture of the driver is designed to allow a large graphic driver pins row1?ow8 driver pins col1?ol8 driver pins col9?ol16 monocolor digit 0 (red*) digit 0 (red*) rows (cathodes) r1 to r8 digit 0 columns (anodes) c1 to c8 monocolor digit 1 (green*) digit 1 (green*) rows (cathodes) r1 to r8 digit 1 columns (anodes) c1 to c8 rgy red/green red/green rows (cathodes) r1 to r8 red columns (anodes) c1 to c8 green columns (anodes) c1 to c8 table 4. standard driver connection to monocolor and rgy 8 x 8 displays * digit 0 of a monocolor display is called red, and digit 1 is called green in the data sheet. red driver0 red red driver1 red red driver2 red red driver3 red red driver4 red red driver5 red red driver6 red red driver7 red red driver8 red red driver9 red red driver10 red red driver11 red red driver12 red red driver13 red red driver14 red red driver15 red red driver16 red red driver17 red red driver18 red red driver19 red red driver20 red red driver21 red red driver22 red red driver23 red figure 1. monocolor 1-bit-per-pixel, 96-pixel x 32-pixel display example
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers _______________________________________________________________________________________ 9 display panel to be driven easily and intuitively by multi- ple max6960s using 8 x 8 cathode-row matrix digits. the max6960s in a display-driver design not only share the host 4-wire interface, but they also share a local 3-wire interface that is not connected to the host. the local 3- wire interface works with the user? driver settings to con- figure all the max6960s to appear to the host interface as one contiguous memory-mapped driver. the pixel level-intensity control uses frame modulation. pixels are enabled and disabled on a frame-by-frame basis over a 12-frame super frame (table 5). the effec- tive pixel frame duty cycle within a super frame sets each pixel? effective intensity. the 12-frame period of a super frame allows arithmetic and geometric intensity scales to be mixed on the same driver. this allows the user to set up an rgy display with a different color scale for red and red driver0 green green green green green green green green green green green green green green green green green green green green green green green green red driver1 red driver2 red driver3 red driver4 red driver5 red driver6 red driver7 red driver8 red driver9 red driver10 red driver11 red driver12 red driver13 red driver14 red driver15 red driver16 red driver17 red driver18 red driver19 red driver20 red driver21 red driver22 red driver23 figure 2. rgy 1-bit-per-pixel 48-pixel x 32-pixel display example column 1 column 2 column 3 column 4 column 5 column 6 column 7 column 8 row 1 row 2 row 3 row 4 row 5 row 6 row 7 row 8 monocolor column 1 (red) row 1 row 2 row 3 row 4 row 5 row 6 row 7 row 8 rgy column 9 (green) figure 3. 8 x 8 matrix pin assignment first display pixel maps to first plane last display pixel maps to last plane memory location figure 4. how plane memory across multiple max6960?ax6963 maps to display pixels
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 10 ______________________________________________________________________________________ green. the max6960 uses display memory planes to store the display images. a memory plane is the exact amount of memory required to store the display image. the memory plane architecture allows one plane to be used to refresh the display, while at least one other plane is available to build up the next image. the global plane counter register (table 30) allows the plane used to refresh the display to be selected either directly on com- mand, or automatically under max6960 control. automatic plane switching can be set from 63 plane changes a second to one plane change every 63s. display memory addressing the max6960 contains 64 bytes of display mapping memory. this display memory provides four memory planes (of 16 bytes) when 1-bit-per-pixel intensity con- trol is selected, or two memory planes (of 32 bytes) when 2-bits-per-pixel intensity control is used (table 6). the 64 bytes of display memory in a max6960 could be accessed with 6 bits of addressing on a driver-by- driver basis. the max6960 uses a 14-bit addressing scheme. the address map encompasses up to 256 max6960 dri- vers, all connected to the host through a common 4- wire interface, and also interconnected through a local 3-wire interface. the purpose of the 3-wire interface is to actively segment the 14-bit address space among the (up to) 256 max6960s. the total display memory is already partitioned among these max6960 drivers in a register format. the max6960s repartition these registers to appear as con- tiguous planes of display memory, organized by color (red, then green) and then into planes (p0 to p4) (table 6). register addressing modes the max6960 accepts 8-bit, 16-bit, and 24-bit trans- missions. all max6960s sharing an interface receive and decode all these transmissions, but the content of a transmission determines which max6960s store and use a particular transmission, and which discard it (table 7). pattern of multiplex cycles for which a pixel is enabled pixel graduation bit bit pixel intensity setting 01234567891011 both 1 1 full 1 1 1 1 1 1 1 1 1 1 1 1 arithmetic 1 0 2/3 1 0 1 1 0 1 1 0 1 1 0 1 geometric 1 0 1/2 1 0 1 0 1 0 1 0 1 0 1 0 arithmetic 0 1 1/3 0 1 0 0 1 0 0 1 0 0 1 0 geometric 0 1 1/4 0 1 0 0 0 1 0 0 0 1 0 0 both 0 0 off 0 0 0 0 0 0 0 0 0 0 0 0 table 5. frame modulation with pixel intensity global panel configuration register planes/intensity (pi bit) color (c bit) pixel-level intensity control display type display mapping addresses per plane display planes available 0 0 1 bit per pixel monocolor 16 red contiguous 4 0 1 1 bit per pixel rgy 8 red contiguous, 8 green contiguous 4 1 0 2 bits per pixel monocolor 16 red contiguous, 16 red contiguous 2 1 1 2 bits per pixel rgy 16 red (2 noncontiguous groups of 8), 16 green (2 noncontiguous groups of 8) 2 table 6. panel configuration
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 11 8-bit transmissions eight-bit transmissions are write-only, data-only accesses that write data to the display memory indi- rected by the global display indirect address register (figure 6). the global display indirect address register autoincrements after the write access. eight-bit trans- missions provide the quickest method of updating a plane of display memory of the max6960. it is the most suitable display update method if the host system builds an image in local memory, and then dumps the image into a display plane of the max6960. 16-bit transmissions sixteen-bit transmissions are read/write, command- and-data accesses to the max6960? configuration registers (figure 7). a write can generally be global (updates all max6960s on the 4-wire bus with the same data) or specific (updates just the max6960 indirected by the global driver indirect address register). note: the global driver indirect address register selects a specific max6960. this is not the same as the glob- al display indirect address register, which points to display memory that could be in any max6960 . a 16-bit read is always indirected through the global dri- ver indirect address register to select only one max6960 to respond. when a read or write is indirect- ed through the global driver indirect address register, the 16-bit command can choose whether the global dri- ver indirect address is autoincremented after the com- mand has been executed. this allows the host to set up one or more registers in consecutive max6960s with the display indirect address, autoincrementing only when required. 8-, 16-, or 24-bit data packet sent to max6960 data format d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 8-bit indirect display memory addressing. address is global display indirect address (14 bits) stored as {msb, lsb} in {register 0x0a, register 0x09}. 8 bits of display memory 16-bit device addressing. r/ w ai l/g 0 4-bit address 8 bits of driver register data factory reserved; do not write to this address. ? 24-bit direct display memory addressing (monocolor 1 bit per pixel). r/ w x planes 0, 1, 2, 3 12-bit addressing across 256 drivers, 4096 x 8 red pixels 8 bits of display memory (1 bit per pixel) 24-bit direct display memory addressing (rgy 1 bit per pixel). r/ w x planes 0, 1, 2, 3 12-bit addressing across 256 drivers, 2048 x 8 red pixels, and 2048 x 8 green pixels 8 bits of display memory (1 bit per pixel) 24-bit direct display memory addressing (monocolor 2 bits per pixel). r/ w x planes 0, 1 13-bit addressing across 256 drivers, 4096 x 4 red pixels 8 bits of display memory (2 bits per pixel) 24-bit direct display memory addressing (rgy 2 bits per pixel). r/ w x planes 0, 1 13-bit addressing across 256 drivers, 4096 x 4 red pixels, and 4096 x 4 green pixels 8 bits of display memory (2 bits per pixel) table 7. register addressing modes
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 12 ______________________________________________________________________________________ 24-bit transmissions twenty-four-bit transmissions are read/write, address- and-data accesses to the max6960? display memory (figure 8). this is direct access to display memory because the memory address is included in the 24-bit transmission, compared with an 8-bit transmission, which uses the memory address stored in the global display indirect address register. twenty-four-bit trans- missions provide the random-access method of updat- ing a plane of display memory of the max6960. it is the most suitable display update method if the host system builds an image directly in a display memory plane, rather than in host local memory. host 4-wire serial interface serial addressing the max6960 communicates to the host through a 4- wire serial interface. the interface has three inputs: clock (clk), chip select ( cs ), and data in (din), and one output, data out (dout). cs must be low to clock data into the device, and din must be stable when sampled on the rising edge of clk. dout is used for read access, and is stable on the rising edge of clk. dout is high impedance except during max6960 read accesses. multiple max6960s may be connected to the same 4-wire interface, with all devices connected to all four interface lines in parallel. the normal limit of paral- leled max6960s is 256, because that is the intercon- nection limit for the 3-wire interface and associated device addressing. the applications information sec- tion discusses some practical issues raised by driving many devices in parallel from the same interface. the serial interface responds to only 8-bit, 16-bit, and 24-bit commands (table 7). the max6960 ignores any transmission that is not exactly 8 bits, 16 bits, or 24 bits between the falling and subsequent rising edge of cs . control and operation using the 4-wire interface controlling the max6960 requires sending an 8-bit, 16- bit, or 24-bit word. the last byte, d7 through d0, is always the data byte. eight-bit accesses are write-only accesses; 16-bit or 24-bit accesses are read or write accesses, as determined by the msb of the transmis- sion, which is set for a read access; clear for a write. a 16-bit or 24-bit read involves transmitting 16 or 24 bits to din, taking cs high, and then reading back 8 bits from dout. only one max6960? dout is enabled from tri-state for readback. the selected max6960? dout normally returns to tri-state after the 8th falling edge of clk. however if cs falls during the read before the 8th falling edge of clk, then the readback is terminated and the selected max6960? dout returns to tri-state. if a number of bits other than exactly 8 bits, 16 bits, or 24 bits are clocked into the max6960 between taking cs low and taking cs high again, then that transmis- sion is ignored. writing device registers the max6960 is written to using the following sequence (figures 3, 4, and 5): 1) take clk low. 2) take cs low. 3) for an 8-bit transmission: clock 8 bits of data into din, d7 first to d0 last, observing the setup and hold times. for a 16-bit transmission: clock 16 bits of data into din, d15 first to d0 last, dn dn-1 t css t ds t dh t cl t ch d1 d0 t cp t csh t csw . t do cs clk din dout d7 d6 d1 d0 t do t do figure 5. timing diagram
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 13 d7 d6 d5 d4 d3 d2 d1 d0 cs clk din dout tri-state figure 6. 8-bit write to the max6960?ax6963 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cs clk din . dout d15 = 0 tri-state figure 7. 16-bit write to the max6960?ax6963 d22 d21 d20 d19 d18 d7 d6 d5 d4 d3 d2 d1 d0 cs clk din dout d23 = 0 tri-state . d14 d13 d12 d11 d10 d9 d8 d16 d15 d17 figure 8. 24-bit write to the max6960?ax6963
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 14 ______________________________________________________________________________________ observing the setup and hold times. bit d15 is low, indicating a write command. for a 24-bit transmission: clock 24 bits of data into din, d23 first to d0 last, observing the setup and hold times. bit d23 is low, indicating a write command. 4) take cs high (while clk is still high after clocking in the last data bit). 5) take clk low. reading device registers any register data within the max6960 may be read by sending a logic-high to bit d15. the sequence is: 1) take clk low. 2) take cs low. 3) for a 16-bit transmission: clock 16 bits of data into din, d15 first to d0 last, observing the setup and hold times. bit d15 is high, indicating a read command. bits d7 to d0 are dummy bits, and are discarded by the max6960. for a 24-bit transmission: clock 24 bits of data into din, d23 first to d0 last, observing the setup and hold times. bit d23 is high, indicating a read com- mand. bits d7 to d0 are dummy bits, and are dis- carded by the max6960. 4) take cs high (while clk is still high after clocking in the last data bit). 5) take clk low. 6) the selected max6960? dout is enabled from tri- state for read back. 7) clock 8 bits of data from dout, d7 first to d0 last, observing the setup and hold times. 8) take clk low after the final (8th) data bit. the selected max6960? dout returns to tri-state. figure 10 shows a read operation when 24 bits are transmitted and 8 bits are read back. local 3-wire serial interface the max6960 uses a 3-wire interface to bus together up to 256 max6960s. the 3-wire bus enables each device to calculate its own unique driver address (0 to 255), and reconfigure its display memory. the addout output also provides an interrupt at every page change, when the plane counter is configured to automatic (table 30). d7 d6 d5 d4 d3 d2 d1 cs clk din dout d15 = 1 tri-state d14 d13 d12 d11 d10 d9 d8 d0 . d7 d6 d5 d4 d3 d2 d1 d0 figure 9. 16-bit read from the max6960?ax6963 d22 d21 d20 d19 d18 d7 d6 d5 d4 d3 d2 d1 cs clk din dout d23 = 1 tri-state d14 d13 d12 d11 d10 d9 d8 d16 d15 d17 d0 . d7 d6 d5 d4 d3 d2 d1 d0 figure 10. 24-bit read from the max6960?ax6963
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 15 3-wire interface data lines (addout and addin) one max6960 is designated the master device, and this is allocated driver address 0. the master? addin pin is connected to v+, identifying it as the first device. this first max6960 should be the driver for the top-left pix- els of the display panel. the master? addout pin is connected to the second max6960? addin pin, and that max6960? addout pin is connect- ed to the third max6960? addin, and so on up to 256 max6960s. the last max6960? addout pin is left open circuit. the last max6960 should be the driver for the bottom-right pixels of the display panel. the addout is initialized low at the start of a 3-wire interface configura- tion operation, and goes high (n + 1.5) addclk periods later, where n is the driver address of the max6960 (0 to 255). see figures 1 and 2 for connection examples. 3-wire interface clock (addclk) the addclk pins for all max6960s are all connected together. addclk data rate is determined by osc / 4, nominally 1.048576 mhz. the addclk pin for the master max6960 (driver address 0) is always an output, and all the other addclks are always inputs. addclk is active for exactly 256 clock cycles when a panel configuration is being performed (on power-up reset, and after a write to the global panel configuration register). use of addout as plane change interrupt (irq) when the plane counter is configured to automatic mode (bit 6 of the global plane counter register is set) (table 30), addout pulses low for a time of 512/osc (nominally 122?) at the start of every automatic plane change. this signal can be used as an interrupt output from the display panel to the host to flag that the previous display plane is now unused and can be written with a new image. multiplex clock the osc input for all max6960s sharing a 3-wire interface bus (but not necessarily a 4-wire interface bus) should be driven by a common cmos-level clock ranging between 1mhz and 8.5mhz. it is usually necessary to use an exter- nal clock tree to fan out multiple clock drives when larger numbers of max6960s are used because of the capaci- tive loads. for example, each one of the eight outputs of a standard 74hc541 octal buffer could drive 8 to 32 max6960 osc inputs, depending on the layout used. the recommended setting for osc is 4.194303mhz. this frequency sets the slow global plane counter resolution to 1s, and the fast global plane counter resolution to 1hz. command address register d15 d14 d13 d12 d11 d10 d9 d8 hex code driver address (read only) x x 0000 0x00 pixel intensity scale x 0001 0x01 panel intensity x 0010 0x02 digit 0 intensity x 0011 0x03 digit 1 intensity x 0100 0x04 fault x 0101 0x05 x0110 0x06 autoincrement local/global x0111 0x07 global driver indirect address* x x x 1000 0x08 global display indirect address lsb* x x x 1001 0x09 global display indirect address xxx1010 0x0a global plane counter* x x x 1011 0x0b global clear planes* x x x 1100 0x0c global panel configuration* x x x 1101 0x0d global driver devices* r/ w xxx1110 0x0e global driver rows* x x x 1111 0x0f table 8. register address map * when reading from the global registers, only the master max6960 (whose driver address is 0x00) responds.
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 16 ______________________________________________________________________________________ global and local register addressing the register map (table 8) contains three local regis- ters and eight global registers. global registers are always written to in all max6960s (on the same 4-wire interface) at the same time, using a 16-bit transmission. a read from a global register also always results in a read from driver address 0. the global nature of these registers ensures that all drivers work together, and there is no chance of a software miss-send causing, for example, multiple max6960s to try to transmit on the 4- wire dout line at the same time. the three local registers can be written to on an individ- ual basis (updates just the max6960 indirected by the global driver indirect address register), or on a global basis (updates all max6960s), according to the status of the local/global bit (table 9). the local/global bit is ignored during a 16-bit read transmission, and the max6960 pointed to by the global driver indirect address register is read. register address autoincrementing when a read or write is indirected through the global dri- ver indirect address register, the 16-bit command can choose whether the global driver indirect address is autoincremented after the command has been executed. command address register address code (hex) d15 d14 d13 d12 d11 d10 d9 d8 local: only the max6960 indirected by driver indirect address is written. 0x0xxxxx global: all max6960s are written with the same data. 0x1xxxxx local: the max6960 indirected by driver indirect address responds. 1x0xxxxx global: the max6960 configured to address 0x00 responds. 0x00 to 0x07 1x1xxxxx global: all max6960s are written with the same data. 0xxxxxxx global: the max6960 configured to address 0x00 responds. 0x08 to 0x0f 1xxxxxxx table 9. register address local/global control bit format command address register address code (hex) d15 d14 d13 d12 d11 d10 d9 d8 driver indirect address is not changed x 0 xxxxxx driver indirect address is incremented after read/write 0x00 to 0x07 x1xxxxxx driver indirect address is not changed 0x08 to xxxxxxxx table 10. register address autoincrement control bit format register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 driver address 0x00 msb 8-bit driver address 0x00 to 0xff lsb table 11. driver address register format
this allows the host to set up one or more registers in consecutive max6960s with the display indirect address, autoincrementing only when required (table 10). driver address register reading the driver address register (table 11) returns the driver address that has been assigned to a particu- lar max6960. the order of the driver addresses is determined purely by the order that the 3-wire interface is daisy-chained through multiple max6960s. the reg- ister is used to detect the presence of a max6960 at an address, and a binary search on the 256 possible addresses can be used to determine the size of an array of max6960s. max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 17 register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 global driver devices 0x0e ms 8-bit global driver devices 0x00 to 0xff lsb table 13. global driver devices format register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 global driver rows 0x0f msb 8-bit global driver rows 0x00 to 0xff lsb table 14. global driver rows format register data register function power-up condition address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 driver address (read only) address 0 0x00 0 0 000000 pixel intensity scale arithmetic for red and green 0x01 x x xxxx00 panel intensity 128/256 intensity 0x02 1 0 000000 digit 0 intensity full 255/256 0x03 1 1 111111 digit 1 intensity full 255/256 0x04 1 1 111111 fault no faults 0x05 0 x xxxx00 global driver indirect address address 0x00 0x08 0 0 000000 global display indirect address lsb 0x09 0 0 000000 global display indirect address msb address 0x0000 0x0a x x 000000 global plane counter manual selection to plane 0 0x0b 0 0 000000 global panel configuration shutdown mode, ripple sync enabled, mux flip enabled, color is mono, 4 display planes/1 bit per pixel 0x0d 0 0 1 1 x x x 0 global driver devices 256 drivers interconnected 0x0e 1 1 111111 global driver rows 256 drivers in a row 0x0f 1 1 111111 table 12. power-up configuration * when reading from the global registers, only the master max6960 (whose driver address is 0x00) responds.
max6960?ax6963 initial power-up the power-up sequence consists of an internal power-on reset (por), assertion of the external reset input rst , and auto-address configuration (see the local 3-wire interface section). the internal por resets all control registers to the default values shown in table 12. after rst goes high an internal timer delays execution of the auto-address configuration for 2 21 (2,097,152) osc cycles (nominally 250ms at osc = 4.194mhz) (see the 3-wire interface clock (addclk ) section). during this delay time, the global driver devices register (0x0e), global driver rows register (0x0f), and global panel con- figuration register (0x0d) should be written as these values are used in the auto-address configuration sequence (see the device configuration section). after the internal delay time, the auto-addressing configuration commences and takes a fixed interval of 256 addclk cycles to complete where the addclk frequency is osc/4 (see the 3-wire interface clock (addclk) sec- tion). after completing the auto-self-addressing of all possible 256 interconnected devices, all of the max6960s enter shutdown mode. all registers are capable of write device register opera- tions during the internal delay interval using the 4-wire serial interface. read device register operations are not allowed during auto-address configuration. 4-wire serially interfaced 8 x 8 matrix graphic led drivers 18 ______________________________________________________________________________________ register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 global panel configuration 0x0d pi c f r dp1 dp0 ip s table 15. global panel configuration register format table 16. global panel configuration?hutdown control (s data bit d0) format register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 logic 1 in display memory lights the appropriate led (normal logic) 0x0d pi c f r dp1 dp0 0 s logic 0 in display memory lights the appropriate led (invert logic) 0x0d pi c f r dp1 dp0 1 s table 17. global panel configuration?nvert pixels (ip data bit d1) format register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 current display plane is p0 0x0d pi c f r 0 0 ip s current display plane is p1 0x0d pi c f r 0 1 ip s current display plane is p2 0x0d 0 c f r 1 0 ip s current display plane is p0 0x0d 1 c f r 1 0 ip s current display plane is p3 0x0d 0 c f r 1 1 ip s current display plane is p1 0x0d 1 c f r 1 1 ip s table 18. global panel configuration?urrent plane (dp0, dp1 data bit d2, d3) format register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 shutdown 0x0d pi c f r dp1 dp0 ip 0 normal operation 0x0d pi c f r dp1 dp0 ip 1
device configuration the max6960s driving a display panel must be config- ured before the panel can be used to display images. the configuration involves the global panel configura- tion register (table 15?able 22), the global driver devices register (table 13), and the global driver rows register (table 14). the global driver devices register should be written with the total number of max6960s interconnected on the 3-wire interface, minus 1 (table 13). for the four panel examples shown in figures 1 and 2, 24 max6960s are used, so the global driver devices register should be written with the value 23, or 0x17. the global driver rows register should be written with the number of max6960s per panel row, minus 1 (table 14). for the panel examples shown in figure 1 and figure 2, there are six max6960s per row, so the global driver rows register should be written with the value 5. the values stored in the global driver devices register and the global driver rows register, together with the c and pl bits in the global panel configuration register (tables 21 and 22), are used by the 3-wire interface configuration engine to reconfigure display memory addressing among the interconnected max6960s. global panel configuration register the global panel configuration register contains eight device settings (table 15 to table 22). shutdown mode (bit d0) shutdown mode is exited by clearing the s bit in the global panel configuration register (table 16). when the max6960 is in shutdown mode, led driver outputs row1?ow8 and col1?ol16 are tri-stated, and multiplexing is halted. data in the global configuration registers remains unaltered. for minimum supply cur- rent in shutdown mode, logic inputs should be at gnd or v+ potential. shutdown mode is exited by setting the s bit in the global panel configuration register. invert pixels (bit d1) the invert pixels (ip) bit in the global panel configura- tion register controls whether the display memory is used directly or inverted (table 17). max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 19 register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 ripple sync is disabled; all interconnected max6960s on the same 4-wire bus resynchronize together. 0x0d pi c f 0 dp1 dp0 ip s ripple sync is enabled; all interconnected max6960s on the same 4-wire bus resynchronize with a 0.9537? delay between adjacent devices. 0x0d pi c f 1 dp1 dp0 ip s table 19. global panel configuration?ipple sync control (r data bit d4) format register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 mux flip is disabled: all interconnected max6960s on the same 3-wire bus resynchronize to the multiplex timing shown in figure 11. 0x0d pi c 0 r dp1 dp0 ip s mux flip is enabled: all interconnected max6960s on the same 3-wire bus resynchronize with max6960s with even driver addresses (0, 2, 4 to 254) operating to the multiplex timing shown in figure 11, and max6960s with odd driver addresses (1, 3, 5 to 255) operating to the flipped multiplex timing shown in figure 12. 0x0d pi c 1 r dp1 dp0 ip s table 20. global panel configuration?ux flip control (f data bit d5) format
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 20 ______________________________________________________________________________________ register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 display panel is built with monocolor or rgb digits (permanently set this way for max6962 and max6963) 0x0d pi 0 f r dp1 dp0 ip s display panel is built with rgy digits 0x0d pi 1 f r dp1 dp0 ip s table 21. global panel configuration?olor control (c data bit d6) format register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 four display memory planes (0, 1, 2, 3) available; pixel level-intensity control is 1 bit per pixel per color (on/off) (permanently set this way for max6961 and max6963) 0x0d 0 c f r dp1 dp0 ip s two display memory planes (0, 1) available; pixel level-intensity control is 2 bits per pixel per color (4 levels) 0x0d 1 c f r dp1 dp0 ip s table 22. global panel configuration?lanes/intensity control (pi data bit d7) format pattern of multiplex cycles for which a pixel is enabled pixel graduation pixel data pixel intensity setting 01234567891011 both 1 1 full 1 1 1111111111 arithmetic 1 0 2/3 1 0 1101101101 geometric 1 0 1/2 1 0 1010101010 arithmetic 0 1 1/3 0 1 0010010010 geometric 0 1 1/4 0 1 0001000100 both 0 0 off 0 0 0000000000 table 23. frame modulation with pixel intensity pattern of multiplex cycles for which a pixel is enabled pixel graduation pixel data pixel intensity setting 01234567891011 both 1 1 full 1 1 1111111111 arithmetic 1 0 2/3 1 0 1101101101 geometric 1 0 1/2 1 0 1010101010 arithmetic 0 1 1/3 0 1 0010010010 geometric 0 1 1/4 0 1 0001000100 both 0 0 off 0 0 0000000000 table 24. pixel intensity scale register format
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 21 2/256th (min on) 3/256th 4/256th 251/256th 252/256th 253/256th 249/256th 250/256th 254/256th (max on) row 0 anode driver intensity settings high-z high-z high-z high-z high-z high-z high-z high-z high-z low low low low low low low low low row/cathode (lit) current source enabled high-z row/cathode (unlit) high-z high-z high-z start of next cycle 122 s timeslot row 0 122 s timeslot row 1 122 s timeslot row 2 122 s timeslot row 3 122 s timeslot row 4 122 s timeslot row 5 122 s timeslot row 6 122 s timeslot row 7 122 s timeslot row 0 row 0's 122 s multiplex timeslot minimum 1.91 s interdigit blanking interval one complete 0.977ms multiplex cycle around 8 rows figure 11. multiplex timing diagram (no flip; osc = 4.194304mhz)
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 22 ______________________________________________________________________________________ start of next cycle 122 s timeslot row 0 122 s timeslot row 1 122 s timeslot row 2 122 s timeslot row 3 122 s timeslot row 4 122 s timeslot row 5 122 s timeslot row 6 122 s timeslot row 7 122 s timeslot row 0 2/256th (min on) 3/256th 4/256th 251/256th 252/256th 253/256th 249/256th 250/256th 254/256th (max on) row 0 anode driver intensity settings high-z high-z high-z high-z high-z high-z high-z high-z high-z low low low low low low low low low row/cathode (lit) current source enabled high-z row/cathode (unlit) high-z high-z high-z row 0's 122 s multiplex timeslot minimum 1.91 s interdigit blanking interval one complete 0.977ms multiplex cycle around 8 rows figure 12. multiplex timing diagram (flipped; osc = 4.194304mhz)
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 23 current plane identification (bits d2, d3) the current plane bits in the global panel configuration register identify which memory plane is currently being used to control the display panel (table 18). these bits are read only; written data is ignored. ripple sync (bit d4) the ripple sync feature, when enabled in the global panel configuration register, desynchronizes the multiplex timing of all the interconnected max6960 drivers on a display panel by osc/4 (table 19). this delay spreads the drive transitions among the drivers to spread power-supply peak-current demand, and ease decoupling. the maxi- mum delay from first driver to last driver is 244? with the maximum of 256 drivers used. this is too short a time to cause visible artifacts. mux flip (bit d5) the mux flip feature in the global panel configuration reg- ister reverses the panel pwm timing for alternate drivers when enabled (table 20). again, this spreads power-sup- ply peak-current demand. color control (bit d6) the color control bit in the global panel configuration reg- ister selects whether a monocolor or rgy display panel is built. select monocolor when building an rgb panel as shown in figure 17. this bit is fixed at zero for the max6962 and max6963, and a write to this bit is ignored for these parts. register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 0/256 0x03 0 0 0 0000 0 1/256 0x03 0 0 0 0000 1 2/256 0x03 0 0 0 0001 0 3/256 0x03 0 0 0 0001 1 4/256 0x03 0 0 0 0010 0 0x03 251/256 0x03 1 1 1 1101 1 252/256 0x03 1 1 1 1110 0 253/256 0x03 1 1 1 1110 1 254/256 0x03 1 1 1 1111 0 255/256 (max on) 0x03 1 1 1 1111 1 table 25. digit 0 intensity register format register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 0/256 0x04 0 0 000000 1/256 0x04 0 0 000001 2/256 0x04 0 0 000010 3/256 0x04 0 0 000011 4/256 0x04 0 0 000100 0x04 251/256 0x04 1 1 111011 252/256 0x04 1 1 111100 253/256 0x04 1 1 111101 254/256 0x04 1 1 111110 255/256 (max on) 0x04 1 1 111111 table 26. digit 1 intensity register format
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 24 ______________________________________________________________________________________ planes/intensity control (bit d7) the planes/intensity (pi) control bit in the global panel configuration register selects whether the display mem- ory is configured as four planes with 1-bit-per pixel per color-intensity control, or two planes with 2-bits-per pixel per color-intensity control. this bit is fixed at zero for the max6961 and max6963, and a write to this bit is ignored for these parts. pixel intensity scale register the pixel intensity scale register (table 24) sets the graduation type used when 2-bits-per-pixel intensity control is selected by setting the pi bit (table 22). the pixel level-intensity control can be set to be either arithmetic (off, 1/3, 2/3, full) or geometric (off, 1/4, 1/2, full). the setting is made on a digit-by-digit basis, so each color on an rgy or rgb panel can use the most appropriate graduation type. digit intensity control the digit 0 and digit 1 intensity registers (tables 25 and 26) set the fractions of the panel intensity pwm value that are applied to the two display digits. the pwm for each digit is calculated as n/256th of the panel intensity value, where n is the value in the digit? digit 0/1 intensi- ty register. the digit 0/1 intensity registers enable con- figuring relative adjustments in digit intensity, while the display panel is still controlled as a whole by the panel intensity. these adjustments are typically used to cali- brate out luminosity differences between leds from dif- ferent batches. they can also be used to color balance rgy displays so that, for example, full panel intensity of a red-green panel is a consistent orange hue. panel intensity control digital control of panel display brightness is provided by an internal pulse-width modulator, which is con- trolled by the panel intensity register (table 27). the modulator scales the average segment current in 253 steps from a maximum of 255/256 down to 2/256 of the peak current. the maximum effective pwm duty cycle for a digit is therefore 254/256, given by the maximum 255/256 digit intensity multiplied by the maximum 255/256 panel intensity. the minimum interdigit blank- ing time is therefore 4/256 of a cycle, or 4/256 x 122? digit period = 1.91?. peak-segment current selection the led drive current can be selected between either a 40ma peak per segment and a lower 20ma peak cur- rent on a digit-by-digit basis using the r iset0 and r iset1 pins. r iset0 should be open circuit to select 20ma, or connected to gnd to select 40ma segment current for digit 0. r iset1 selects segment current for register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 global driver indirect address 0x08 msb 8-bit driver indirect address 0x00 to 0xff lsb table 28. global driver indirect address format register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 0x02 0000000 0 0x02 0000000 1 2/256 (min on) 0x02 0000001 0 3/256 0x02 0 0 00001 1 4/256 0x02 0 0 00010 0 5/256 0x02 0 0 00010 1 0x02 251/256 0x02 1 1 11101 1 252/256 0x02 1 1 11110 0 253/256 0x02 1 1 11110 1 254/256 0x02 1 1 11111 0 255/256 (max on) 0x02 1 1 11111 1 table 27. panel intensity register format
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 25 register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 global display indirect address lsb 0x09 d7 d6 d5 d4 d3 d2 d1 d0 global display indirect address msb 0x0a x x d13 d12 d11 d10 d9 d8 table 29. global display indirect address format register data register planes/intensity bit (see table 22): 0 for 1 bit/pixel; 4 planes 1 for 1 bit/pixel; 4 planes address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 plane counter 0x0b fast slow auto manual counter setting manual selection to plane 0?ounter disabled x 0x0b x 0 x x x x 0 0 manual selection to plane 1?ounter disabled x 0x0b x 0 x x x x 0 1 manual selection to plane 2?ounter disabled 0 0x0b x 0 x x x x 1 0 manual selection to plane 0?ounter disabled 1 0x0b x 0 x x x x 1 1 manual selection to plane 3?ounter disabled 0 0x0b x 0 x x x x 1 0 manual selection to plane 1?ounter disabled 1 0x0b x 0 x x x x 1 1 slow plane counter 0 1 xxxxxx auto slow plane counter? frame every second 0x0b 0 1 0 0 0 0 0 1 auto slow plane counter? frame every 2s 0x0b 0 1 0 0 0 0 1 0 0 1 auto slow plane counter? frame every 62s 0x0b 0 1 1 1 1 1 1 0 auto slow plane counter? frame every 63s 0x0b 0 1 1 1 1 1 1 1 fast plane counter 1 1 xxxxxx auto fast plane counter? frame per second 0x0b 1 1 0 0 0 0 0 1 table 30. global plane counter register format
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 26 ______________________________________________________________________________________ digit 1 in the same manner. the max6960 is guaran- teed to drive 40ma peak segment current into a 2.4v led with a minimum supply voltage of 3.15v, and 20ma peak segment current into a 2.2v led with a minimum supply voltage of 2.7v. global driver indirect address register the global driver indirect address register is used to store the driver address identifying which of 256 max6960s is accessed for 16-bit transmission when a local register is read (table 28). global display indirect address register the global display indirect address registers are used to store the 14-bit display memory address identifying which byte of display memory across all the intercon- nected max6960s is written by an 8-bit transmission (table 29). the 14-bit address stored in these two reg- isters increments after every 8-bit transmission, and overflows from address 0x3fff to address 0x0000. global plane counter the global plane counter (table 30) allows any display plane to be selected as the current display plane, or configures the max6960 for automatic plane sequenc- ing. the display plane is switched to the newly selected plane on the rising edge of cs at the end of the 16-bit transmission. when automatic plane sequencing is selected, the current display plane is initialized to plane p0. the current display plane is incremented through all four planes p0?3 (planes/intensity = 0) or both planes p0?1 (planes/intensity = 1) at the frame rate selected, and then restarts at plane p0 again. the plane sequencing continues until the global plane counter is reconfigured. if the global plane counter is used for the automatic sequencing of animations, the user should ensure that the plane ahead of the current display plane is updated before the automatic plane switchover to achieve artifact-free animation. global clear planes command writing the global clear planes counter (table 31) allows any or all display memory planes to be cleared with one command. the selected plane(s) are cleared on the ris- ing edge of cs at the end of the 16-bit transmission. fault detection led fault detection the max6960 detects open-circuit and short-circuit leds. it can only detect an led fault when attempting to light that led, so a good strategy to check a panel is to program the panel with all leds on power-up to check the displays. the fault and device id register (table 32) uses 3 bits to flag and distinguish open-circuit (open flag), short circuit (short flag), and overtemperature (ot flag) faults, and a fourth flag (fault flag), which is an or of the open flag, short flag, and ot flag. the fault and device id register is cleared on power- up, and can also be cleared by writing to it. the fault flags are not cleared by a read. when writing the fault and device id register, the data written is ignored; all fault flags are cleared, including the ot flag. it is possi- ble to clear all max6960s on a bus by performing a global write to the fault and device id register. register data register planes/intensity bit (see table 22): 0 for 1 bit/pixel; 4 planes 1 for 1 bit/pixel; 4 planes address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 plane counter 0x0b fast slow auto manual counter setting auto fast plane counter? frames per second 0x0b 1 1 0 0 0010 1 1 auto fast plane counter?62 frames per second 0x0b 1 1 1 1 1110 auto fast plane counter?63 frames per second 0x0b 1 1 1 1 1111 table 30. global plane counter register format (continued)
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 27 register data register address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 fault (read) 0x05 fault flag part id x x ot flag short flag open flag fault (write) clears fault register status 0x05 0 part id x x 0 0 0 device is max6960 0x05 x 0 0 x x x x x device is max6961 0x05 x 0 1 x x x x x device is max6962 0x05 x 1 0 x x x x x device is max6963 0x05 x 1 1 x x x x x no led or ot faults 0x05 0 part id x x 0 0 0 at least one open-circuit led fault 0x05 1 part id x x x x 1 at least one short-circuit led fault 0x05 1 part id x x x 1 x overtemperature fault 0x05 1 part id x x 1 x x table 32. fault and device id register format register data action address code (hex) d7 d6 d5 d4 d3 d2 d1 d0 global clear planes 0x0c green p3 green p2 green p1 green p0 red p3 red p2 red p1 red p0 clear all red plane p0 display memory 0x0c x xxxxxx1 clear all red plane p1 display memory 0x0c x xxxxx1x clear all red plane p2 display memory* 0x0c x xxxx1xx clear all red plane p3 display memory* 0x0c x x x x 1 x x x clear all green plane p0 display memory ? 0x0c x x x 1 x x x x clear all green plane p1 display memory ? 0x0c x x 1 xxxxx clear all green plane p2 display memory ?* 0x0c x 1 xxxxxx clear all green plane p3 display memory ?* 0x0c 1 xxxxxxx table 31. global clear planes register format * these bit settings are ignored when the global panel configuration register bit pi is clear (i.e., ignored in 2-bits-per-pixel mode). ? these bit settings are ignored when the global panel configuration register bit c is clear (i.e., ignored in monocolor mode).
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 28 ______________________________________________________________________________________ overtemperature fault detection the max6960 contains an overtemperature (ot) detec- tion circuit, which trips at a die temperature of typically +150?. the ot event is latched, and is readable in the fault and device id register (table 32). when the ot trips, the max6960 shutdown bit in the configuration register (table 15) is cleared, and the driver goes into shutdown. data is not lost; the effect is the same as the user setting the shutdown bit. the user can attempt to set the shutdown bit at any time. however, if the driver is still over temperature, then the attempt to set the shutdown bit is ignored. the ot fault flag is not auto- matically cleared when the device cools, or when the device is taken out of shutdown. the fault and device id register is cleared on power- up, and can also be cleared by writing to it. the fault flags are not cleared by a read. when writing the fault and device id register, the data written is ignored; all fault flags are cleared, including the led flags. it is possible to clear all max6960s on a bus by performing a global write to the fault and device id register. applications information setting led drive current the max6960 can be configured for pretrimmed 20ma or 40ma led current, or a 20ma to 40ma adjustable current, on a digit-by-digit basis by the riset0 and riset1 pin connections (figures 13 and 14). the digit intensity registers can be used to digitally adjust the segment current, again on a digit-by-digit basis, by controlling the pwm. some applications best use one or the other technique; some applications may require the flexibility of both. v ref to red led drivers r int r int riset0 42 v ref to green led drivers r int r int riset1 43 max6960 max6961 max6962 max6963 figure 13. riset0 and riset1 internal architecture max6960 max6963 max6960 max6963 max6960 max6963 42 43 riset0 riset1 42 43 riset0 riset1 42 43 riset0 riset1 no connection no connection r0 r1 setting led current to 40ma adjustable led current 20ma setting led current to 20ma figure 14. riset0 and riset1 pin connections
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 29 power supplies the max6960 operates from a single 2.7v to 3.6v power supply. accuracy of the led drive current of 20ma is guaranteed over this supply range. accuracy of the led drive current of 40ma is guaranteed over a supply range of 3.15v to 3.6v. bypass each of the 5 v+ power-supply pins to gnd with a 0.1? capacitor as close to the device as possi- ble. add a 10? to 100? bulk decoupling capacitor to the supply bus at least every several max6960s. each max6960 draws a peak current of either 40ma x 16 segments = 640ma (current setting = high) or 20ma x 16 segments = 320ma (current setting = low), regard- less of the pwm plane and pixel intensity settings. if ripple sync and/or mux flip are enabled, then the timing of these peak currents is desynchronized between dri- vers, providing an easier load to the power supply. for all but the smallest display panels, it is necessary to use 2oz copper boards to minimize the voltage drops across the supply planes with the high currents that are required. set the supply voltage to 3.6v at the panel supply input to allow the most margin for on-board sup- ply voltage drops. for the tqfn package, connect the exposed pad to gnd. rst input the external reset input, rst , is asserted low and halts internal operations and forces control registers to their default values shown in table 12. in systems where the max6960s are operated from different regulated sup- plies with different power-up delays, hold rst of every interconnected max6960 low until 50ms after the last max6960 has powered up. rst can be asserted low at any time to force all devices to the default condition. rst must be driven by a cmos logic output supplied by v+. a supervisor, such as the max6821x526, which has an adjustable power-up reset delay, is a good choice. when rst is deasserted, the sequence of events for writing global registers and auto-address configuration is the same as described in the initial power-up section. package dissipation typical full-power (all segments on) device power dissi- pation is 671mw (v+ = 3.3v, v led = 2.3v, i led = 40ma, 254/256 full intensity). consider the effect of one or more shorted display leds in planning dissipation handling. the max6960 remains under the 1023mw mqfp package dissipation limit at +70? with v+ = 3.6v and v led = 2.1v. the tqfn package is preferred for 40ma segment current applications because the 2.16w package dissipation limit easily handles worst- case applications including multiple shorted leds. connecting multiple max6960s to the 4-wire bus up to 256 max6960s can be interconnected to share the same 4-wire bus in parallel, sharing a common cs . the maximum of 256 devices is set by the automatic address allocation limit. care is needed to achieve the successful parallel interconnection of more than 16 max6960s due to the high-capacitive loading this pre- sents onto the 4-wire bus. it is generally necessary to either buffer and drive the clk, din, and cs lines to small groups of drivers, or to reduce the 4-wire data rate from the 20mb/s limit, if more than approximately 16 max6960s are used. the exact limit depends on the application? 4-wire data rate requirement, the capaci- tive drive capability of the host? clk, din, and cs dri- vers, and the effective capacitance of the clk, din, and cs routing on the circuit board. the circuit in figure 15 shows one way of fanning out the clk, din, and cs lines to 128 max6960s, and fanning in the dout lines back into one dout line. the clk, din, and cs lines are buffered with standard cmos bus buffers, with each buffer output driving 16 clk, din, or cs inputs. the tri-state dout outputs are also connect- ed together in groups of 16, and fed into octal analog multiplexers. the analog multiplexers are used here as data selectors, with the very low (10 ) switch resis- tance providing an effective logic power driver. note, however, that while the max6960? dout output is tri- state, the selected dout from this power driver is not. using the max6960 as controller for higher voltage or higher current the max6960 can be used as a graphic controller with external drive transistors for applications requiring higher peak segment currents and/or a higher drive voltage (multiple leds in series for each pixel). the panel and pixel-level intensity control is still available because pwm techniques are used, but the peak seg- ment current is set by external current-limiting resistors in series with the leds, instead of the max6960? inter- nal precision constant-current sources. figure 16 shows example output drivers that interface the max6960 to control anode-row displays at a higher segment current and drive voltage. sixteen instances of the low-current cathode column driver, and eight instances of the high-current anode row driver are required per max6960.
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 30 ______________________________________________________________________________________ 0?5 16?1 32?7 48?3 64?9 80?5 96?11 112?27 din din drivers 1 19 2 3 4 5 6 7 8 9 g1 g2 a1 a2 a3 a4 a5 a6 a7 a8 18 17 16 15 14 13 12 11 y1 y2 y3 y4 y5 y6 y7 y8 ic1a 74vhc541 0?5 16?1 32?7 48?3 64?9 80?5 96?11 112?27 cs drivers 1 19 2 3 4 5 6 7 8 9 g1 g2 a1 a2 a3 a4 a5 a6 a7 a8 18 17 16 15 14 13 12 11 y1 y2 y3 y4 y5 y6 y7 y8 ic2a 74vhc541 0?5 0?5 16?1 32?7 48?3 64?9 80?5 96?11 112?27 15?1 32?7 48?3 64?9 80?5 96?11 112?27 clk clk drivers 1 19 2 3 4 5 6 7 8 9 g1 g2 a1 a2 a3 a4 a5 a6 a7 a8 a y b w c d e f g h 18 17 16 15 14 13 12 11 18 17 16 15 14 13 12 11 y1 y2 y3 y4 y5 y6 y7 y8 ic3a 74vhc541 ic8 74ac4078 cs 48?3 64?9 80?5 13 14 12 1 5 2 4 6 11 x0 x1 x3 x4 x5 x6 x7 inh a 3 x 10 9 15 x2 b c max4617 ic6a 0v 0v 0v 0v dout drivers 1k 1k 1k 96?11 112?27 13 14 12 1 5 2 4 6 11 74lv27 1 13 10 9 8 11 x0 x1 x3 x4 x5 x6 x7 inh a 3 x 10 9 15 x2 b c v+ max4617 0v 0v 0v dout drivers 1k 1k 0?5 16?1 32?7 13 14 12 1 5 2 4 6 11 x0 x1 x3 x4 x5 x6 x7 inh a 3 x 10 9 15 x2 b c max4617 ic5a 0v 0v 0v 0v dout drivers 1k 1k 1k dout 5 74lv27 4 3 6 13 74lv27 ic7a ic7b ic7c 2 1 12 v+ v+ figure 15. max6960?ax6963 high-speed 4-wire interface expansion
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 31 to use these drivers, choose r1 to set the desired peak segment current i peak according to the driver supply voltage v driver and the led forward voltage drop v led : i peak = (v driver - v led - v ce(sat)q1 ) / (r1 + r ds(on)q2 ) a choose r2 to pass 5ma in order to drop 5v across r3 to provide 5v gate drive to logic-level pfet q2: r2 = (v driver - v ce(sat)q3 - 5) x 200 rate q1 at segment current i peak , and rate q2 at row current, which is 16 times i peak . using the max6960 as driver/controller for rgb displays a max6960 can drive an 8 x 16 led matrix, and so one max6960 can drive two 8 x 8 monocolor digits or one 8 x 8 rgy digit. a max6960 cannot directly drive an 8 x 8 rgb display digit, but max6960s can nevertheless be used to build rgb panels. the max6960 drivers provide 3 x 2 = 6 bits of color control to an rgb panel, or 64 colors. the best way to drive rgb leds with the max6960 is to use three 3-wire buses, one for each color (figure 17). a single 4-wire interface must be used, with three cs s, again one for each color. the red and green leds are driven directly by their max6960s, and are connected cathode row as normal. the blue leds cannot be driven directly by their max6960s because the blue led for- ward voltage is too high, so external drive transistors must be used as discussed previously. the blue leds are therefore connected anode row. the max6960 is suitable to drive discrete rgb matrix displays using either separate leds for the red, green, and blue or six- terminal surface-mount or through-hole rgb leds. the six-terminal leds must be used to give individual access to the anodes and cathodes. the max6960 is not suit- able to drive prewired rgb 8 x 8 matrix displays because the row/column wiring is incorrect. synchronization is achieved by writing the global panel configuration registers for every driver at the same time. the user must therefore provide a method for dri- ving all three cs s together when writing the global panel configuration register. this complexity aside, the three-bus method automatically organizes the display memory into three color planes. also, ripple sync and mux flip can be enabled or disabled in any manner desired. the digit limit for one set of three 3-wire buses is 768 rgb digits using 256 max6960s. the structure can be repeated to build a very large panel. max6960-max6963 connect exposed pad (tqfn only) to gnd. top view tqfn 7mm x 7mm 12 13 14 15 16 17 18 19 20 21 22 gnd osc cs din dout clk rst col1 col2 col3 v+ 44 43 42 41 40 39 38 37 36 35 34 1 2 345678910 11 gnd riset1 riset0 addclk addin addout v+ col16 col15 col14 v+ gnd row8 row7 row6 row5 gnd row4 row3 row2 row1 gnd 33 32 31 30 29 28 27 26 25 24 23 col4 col5 col6 col7 col8 v+ col9 col10 col11 col12 col13 pin configurations (continued) v driver v driver q2 q3 q1 v+ ov 0v 0v g s d r4 47k r1 r6 820 r5 820 r3 1k r2 row1?ow8 col1?ol16 anode row drive (1 of 8) cathode column drive (1 of 16) figure 16. current and voltage boosting max6960?ax6963 with external transistors
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 32 ______________________________________________________________________________________ max6960 addin addout max6960 addin addout max6960 addin addout 3.3v anode rows (digits 0, 1) cathode columns digit 0 red digit 1 red anode rows (digits 2, 3) cathode columns digit 2 red digit 3 red anode rows (digits 4, 5) cathode columns digit 4 red digit 5 red to next max6960 max6960 addin addout max6960 addin addout max6960 addin addout 3.3v cathode columns digit 0 green digit 1 green cathode columns digit 2 green digit 3 green cathode columns digit 4 green anode rows (digits 0, 1) anode rows (digits 2, 3) anode rows (digits 4, 5) anode rows (digits 0, 1) blue row1?ow8* anode rows (digits 2, 3) blue row1?ow8* anode rows (digits 4, 5) blue row1?ow8* *see figure 16 digit 5 green to next max6960 max6960 addin addout max6960 addin addout max6960 addin addout 3.3v cathode columns digit 0 blue col1?ol8* digit 1 blue col9?ol16* cathode columns digit 2 blue col1?ol8* digit 3 blue col9?ol16* cathode columns digit 4 blue col1?ol8* digit 5 blue col9?ol16* to next max6960 row1?ow8 col0?ol8 col9?ol16 row1?ow8 col0?ol8 col9?ol16 row1?ow8 col0?ol8 col9?ol16 row1?ow8 col0?ol8 col9?ol16 row1?ow8 col0?ol8 col9?ol16 row1?ow8 col0?ol8 col9?ol16 row1?ow8 col0?ol8 col9?ol16 row1?ow8 col0?ol8 col9?ol16 row1?ow8 col0?ol8 col9?ol16 figure 17. connecting max6960?ax6963s to rgb displays
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers ______________________________________________________________________________________ 33 package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) mqfp44.eps d 1 1 21-0826 package outline 44l mqfp, 1.60 lead form
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers 34 ______________________________________________________________________________________ 32, 44, 48l qfn .eps e l e l a1 a a2 e/ 2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k package outline 21-0144 2 1 f 32, 44, 48, 56l thin qfn, 7x7x0.8m m package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .)
max6960?ax6963 4-wire serially interfaced 8 x 8 matrix graphic led drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 2007 maxim integrated products is a registered trademark of maxim integrated products, inc. package outline 21-0144 2 2 f 32, 44, 48, 56l thin qfn, 7x7x0.8m m package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) revision history pages changed at rev 2: 1, 3, 35 pages changed at rev 3: 1, 32, 35 chip information transistor count: 120,579 process: bicmos

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